In past years, integrated semiconductor circuits, in particular memory components, have been able to be embodied with ever higher levels of integration by virtue of planar-lithographic patterning methods that have continually been improved further, so that the required chip sizes have been able to be reduced. These so-called “shrinks” have enabled semiconductor circuits to be produced more and more cost-effectively. Equally, however, the production process for such integrated semiconductor circuits has become more complex, whereby testing of the semiconductor circuits produced is acquiring ever greater importance. In order to test memory components, in particular DRAMs, a widespread procedure is to integrate self-test structures on the memory chip. Such self-test structures, which are also referred to as built-in self-test (BIST), simplify and accelerate the functional test method for the memory module to a significant extent.
However, the integration of such BIST structures on the memory chip leads to an enlargement of the required chip area which gives rise to cost disadvantages in production.